1. Technical Field
The present invention disclosed herein relates to a flash memory device and more particularly, to a multi-bit flash memory device and a program method thereof.
2. Discussion of the Related Art
Semiconductor memory devices may be volatile or nonvolatile. Volatile memory devices may be written to and read from relatively quickly, but lose data when external power is discontinued. Nonvolatile memory devices retain data even after external power has been discontinued. Therefore, nonvolatile memory devices are employed to store data that should be retained regardless of whether power is supplied. Such nonvolatile memory devices include mask read-only memory (MROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), and so forth.
Generally, it is not easy for a system using MROM, PROM and/or EPROM to update data stored therein. EEPROMs are widely employed in systems where data is frequently updated since they are electrically erasable and programmable. Flash EEPROMs offer higher integration density than conventional EEPROMs, and may thus be used in storage units with large storage capacity. In particular, NAND-type flash EEPROMs (hereinafter, referred to as ‘NAND flash memory’) have a particularly high integration density.
In recent years, with increasing demand for high-integration memory devices, multi-bit memory devices storing multiple bits of data in a unit cell are disclosed, for example, in U.S. Pat. No. 7,035,144 entitled “FLASH MEMORY DEVICE HAVING MULTI-LEVEL CELL AND READING AND PROGRAMMING METHOD THEREOF”, U.S. Pat. No. 6,082,056 entitled “FLASH MEMORY DEVICE AND ARCHITECTURE WITH MULTI LEVEL CELLS”, and U.S. Pat. No. 5,923,587 entitled “MULTI-BIT MEMORY CELL ARRAY OF A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME”, which are all incorporated herein by reference.
When storing 1-bit data in a memory cell, the memory cell is conditioned in one of two threshold-voltage distributions, for example, corresponding to either a data states ‘1’ or a data state ‘0’. When storing 2-bit data in a memory cell, the memory cell is conditioned in one of four threshold voltage distributions. When storing 3-bit data in a memory cell, the memory cell is conditioned in one of eight threshold voltage distributions. Techniques are presently being developed for storing 4-bit data in a unit memory cell.
FIG. 1 shows a scheme for programming a 4-bit cell. Threshold-voltage distribution profiles show programming steps for programming multi-bit memory cells having 16 threshold voltage states. Here, the data ordering patterns corresponding to the threshold voltage states are featured in the Gray coding arrangement where one bit is converted to another bit during a single programming step. Referring to FIG. 1, the programming operation is carried out by including first through fourth page programming steps (Page-1 program—Page-4 program) that write 4-bit data from a least significant bit (LSB) to a most significant bit (MSB). Each bit of the 4-bit data is input in units of a single page written by the programming operation of one cycle. FIG. 1 shows a programming operation for a multi-bit flash memory device. Here, the multi-bit memory is programmed in 4 pages. The final page (4th page) corresponds to the most significant bit (MSB) page.
In programming the MSB page, the multi-bit flash memory device conducts an initial reading operation for reading programmed results of the previous pages of the memory cells. After finding threshold voltage locations of the memory cells by means of the initial reading operation, the MSB page is programmed with reference to the threshold voltage locations. The initial reading operation for the fourth page programming step is conducted with voltages IRD1-IRD7 (referenced as 10) that are supplied to a word line of the memory cells. After completing the initial reading operation, the multi-bit flash memory device begins to program the memory cells in accordance with a logical value (‘1’ or ‘0’) of the MSB page. After the programming operation 20, a verifying operation is carried out to determine whether the programming operation 20 has been completed, using verifying voltages 30 corresponding to each of the threshold voltage states. Through the verifying operation, memory cells that have not been fully programmed in a target state of threshold voltages are detected. The memory cells detected as being under-programmed are re-programmed. This repetition of programming and verifying operations continues until all of the memory cells are detected as having passes the verifying operation.
Throughout the programming steps for the pages as shown in FIG. 1, program disturbance due to capacitive coupling effects may be present as relatively high voltages are applied to selected word lines. Further, electrons injected into floating gates by the programming operation may dissipate over time. In this case, the threshold voltage distributions of the memory cells may extend upward or downward.
FIG. 2 shows an extension of the threshold voltage distributions during the programming operation. Referring to FIG. 2, threshold voltage states ‘010’ and ‘011’ are shown having an extended distribution after the third page programming step. The threshold voltage states ‘010’ and ‘011’ include overlapping regions 30 and 40 caused by the extended threshold voltage distributions. Here, the threshold voltage states ‘010’ and ‘011’ are set to be ‘1010’ and ‘1011’ by program inhibition when the fourth page data (or MSB) is ‘1’. Before the programming operation for the fourth page data, the memory cells corresponding to the threshold voltage states are targeted for the initial reading operation, being read by means of the read voltage IRD7. Unless the initial reading operation is accurately carried out, the reliability of the programming operation with the fourth page data is reduced.
However, the overlapping regions 30 and 40 generated from the threshold voltage states ‘010’ and ‘011’ may cause an erroneous result of the initial reading operation. As illustrated in FIG. 2, memory cells corresponding to the overlapping region 30 are normally included in the threshold voltage state ‘011’. According to the initial reading operation with the read voltage IRD7, the memory cells included in the overlapping region 30 will be read out in the threshold voltage state ‘010’. The memory cells with 3-bit initial read data of ‘010’ are programmed in the threshold voltage state ‘0010’ when the fourth page data (or MSB) is ‘0’. The memory cells with 3-bit initial read data of ‘010’ are programmed in the threshold voltage state ‘1010’ when the fourth page data (or MSB) is ‘1’. These programming errors may also occur in the memory cells included in the overlapping region 40.
FIG. 3 is a table summarizing programmed results according to the initial reading operation for the memory cells included in the overlapping regions 30 and 40.
Referring to FIG. 3, due to extension of the threshold voltage distributions, the memory cells of the overlapping region 30 are detected as being in the threshold voltage state ‘010’ by the initial reading operation that looks at the programmed result of the third page. Thus, the memory cells included in the overlapping region 30 are programmed in the threshold voltage states ‘0010’ when the fourth page data is ‘0’. Without extension of the threshold voltage distributions, the memory cells of ‘010’ are programmed in the threshold voltage state ‘0011’. The memory cells included in the overlapping region 30 are programmed in the threshold voltage states ‘1010’ when the fourth page data is ‘1’. Without extension of the threshold voltage distributions, the memory cells of ‘011’ are programmed in the threshold voltage state ‘1011’.
The memory cells of the overlapping region 40 are detected as being in the threshold voltage state ‘011’ through the initial reading operation. Thus, the memory cells included in the overlapping region 40 are programmed in the threshold voltage states ‘0011’ when the fourth page data is ‘0’, or programmed in the threshold voltage states ‘1011’ when the fourth page data is ‘1’. Without extension of the threshold voltage distributions, the memory cells of ‘011’ are programmed in the threshold voltage state ‘0010’ or ‘1010’.
As can be seen from the aforementioned figures, data erroneously read through the initial reading operation of the multi-bit flash memory device may affect the programming operation. While the aforementioned figures illustrate the programming operation for the MSB pages, erroneous results from the initial reading operation are not limited to the types of errors shown. For instance, extension of threshold voltage distributions may occur during a programming operation for the second page (Page-2) or the third page (Page-3). Furthermore, an initial read error is not limited to being caused by extension of threshold voltage distributions in the memory cells. Other reasons, such as noises arising while reading data, may also cause initial read errors. For example, an initial read error arising from a programming operation for the second page (Page-2) affects a programming operation for data of the third page (Page-3) or the fourth page (Page-4). Therefore, a 1-bit error generated from the initial reading operation may give rise to a 2-bit or 3-bit error.